1. Field of the Invention
The present invention relates to a computer system with a multiprocessor configuration and more particularly to a control unit for a computer system comprising a plurality of CPUs having different instruction properties.
2. Description of Related Art
In a conventional computer system with a multiprocessor configuration, all the CPUs have equivalent functions and properties and these CPUs are utilized without discrimination by an operating system according to the dispatching function, as in the technique disclosed in "ACOS-4/XVP Supervisor Reference Manual", DDA82E-2, NEC Corporation, 1992, pp. 3-33 to 3-34.
Moreover, in the technique disclosed in pp. 9-7 to 9-12 of the above-mentioned "Supervisor Reference Manual", all the CPUs are treated equivalently also in the fault recovery processing of the CPUs.
Furthermore, there exists an asymmetric system mode, as disclosed in Hwang et al., "Computer Architecture Parallel Processing", McGraw-Hill, 1985, pp. 684-692, in which an attached processing unit having a role different from that of the CPUs is utilized as an attached processor.
In the aforementioned conventional computer system consisting of CPUs having an equivalent instruction property, it is not possible to execute at high speed, both of, for example, a program aimed mainly at scientific computations and a program aimed mainly at office processing, which leads to a drawback in that it is necessary to prepare dedicated computer systems for respective programs.
In addition, in the computer system with the attached processor mode, it has a drawback in that it can execute only specific functions and since a program to be executed by means of attached processors is described in an instruction configuration of CPUs suitable for the property concerned, it has a problem in that when an attached processor becomes unusable due to a fault, the program becomes inoperative even if other CPUs are operating normally.